As is well known, throughput of networks can degrade if internal network buffers fill up. Full buffers in one part of the network can prevent other packets from passing through that part of the network. Algorithms such as TCP/IP use “pacing”, or window flow control algorithms, to limit the number of packets in the network; this can improve throughput. These algorithms use acknowledgement packets to grant a sender permission to send additional packets. However, the software overhead to implement such algorithms is excessive in a scientific parallel computing environment where high throughput and low latency are essential.
Thus, it is desirable to have a pacing mechanism that can be integrated into the hardware that would eliminate software overhead.